This invention relates to semiconductor memory devices and more particularly to a dynamic memory device of the type having multiplexed row and column addresses.
The most widely used semiconductor memory devices at present are large scale arrays of one-transistor dynamic memory cells of the type described in U.S. Pat. No. 3,940,747, issued Feb. 24, 1976, to Kuo and Kitagawa, assigned to Texas Instruments. Higher density versions of these memory systems are shown in Electronics, May 13, 1976, pp. 81-86. These high density devices use one-transistor dynamic memory cells which have the advantage of very small size, and thus low cost, but have the disadvantage of requiring external refresh systems. Each row of an array of cells must be addressed periodically to restore the data, since the stored voltages will leak off the capacitors in the memory cells. Refresh imposes both time and hardware burdens on the system.
Usually refresh is accomplished by sequentially accessing all rows of a dynamic RAM, and in typical devices with multiplexed row and column addresses only the row address strobe signal is applied, not the column address strobe signal. Thus, internal clocks based on the column address strobe signal will deteriorate.
It is the object of this invention to provide an improved refresh operating mode in a dynamic RAM of the type having multiplexed row and column addresses, particularly to prevent decay of voltage levels of internal clocks.